FPGA(3)                                                   FPGA(3)

          fpga - interface to on-board FPGA

          bind -a #F /dev


          Fpga allows configuration of an on-board FPGA (eg, the
          Altera Flex6000 on the Bright Star Engineering ip-Engine),
          control of its clocks and environment, and raw access to any
          devices presented in the FPGA address space.  On booting,
          the FPGA subsystem is normally left powered down and the
          system's external clocks are not directed to the processor's
          output pins, to conserve power if the subsystem is unused.

          The control file fpgactl accepts the following requests:

          bclk n     Set BCLK output to n MHz, where n must be a divi-
                     sor of the system clock frequency (eg, of 48 if
                     the system is running at 48 MHz).
          power      Power up the FPGA subsystem (that is automati-
                     cally done when fpgaprog is accessed).
          power off  Power down the FPGA subsystem.
          reset      Reset the FPGA, forcing it into configuration
                     mode (automatically done when fpgaprog is
          vclk n m v r
                     Program the clock synthesiser with the given
                     parameters, and enable its output as VCLK.
          vclk off   Disable output from the clock synthesiser.

          The files fpgamemb and fpgamemw give 8-bit and 16-bit access
          respectively to the address space interpreted by the FPGA.
          The file offset is the address read or written within that
          space; offset and count must both be even for fpgamemw.  The
          interpretation of the data, including the data format and
          whether byte or word access is required, is completely
          determined by the program configured into the FPGA.

          The write-only file fpgaprog configures the device.  A sin-
          gle write provides an FPGA configuration in raw binary for-
          mat.  The FPGA subsystem is given power, the processor's
          clocks are made visible externally, and the device is

     FPGA(3)                                                   FPGA(3)

          configured with the data written.  The write returns an
          error if configuration fails.

          The read-only file fpgastatus contains a single line of text
          giving the state of the two status bits in the FPGA inter-
          face.  The word config appears if CONFIG_DONE is set, and
          !config otherwise; the word status appears if nSTATUS is
          set, and !status otherwise.